Heavy Reading竞争分析：网络处理器研究报告(Network Processors A Heavy Reading Competitive Analysis)

I. INTRODUCTION AND KEY FINDINGS
　　1.1 Key Findings
　　1.2 Report Scope and Structure

II. NPU MARKET AND APPLICATIONS
　　2.1 Leading Applications
　　2.2 Vendor Summary

III. CONTROL-PLANE PROCESSORS
　　3.1 Control-Plane Processors in Production
　　3.2 Recently Announced Control-Plane Processors
　　3.3 Control-Plane Processor Architectures
　　3.4 Control-Plane Processor I/O

IV. COMMUNICATIONS PROCESSORS
　　4.1 Communications Processors in Production
　　4.2 Recently Announced Communications Processors
　　4.3 Communications Processor I/O
　　4.4 Communications Processor Features

V. 2.5-GBIT/S NPUS
　　5.1 2.5-Gbit/s NPUs in Production
　　5.2 Recently Announced 2.5-Gbit/s NPUs
　　5.3 2.5-Gbit/s NPU Embedded Controllers
　　5.4 2.5-Gbit/s NPU Architectures
　　5.5 2.5-Gbit/s NPU Memory
　　5.6 2.5-Gbit/s NPU I/O
　　5.7 2.5-Gbit/s NPU Traffic Management

VI. 10-GBIT/S NPUS
　　6.1 10-Gbit/s NPUs in Production
　　6.2 Recently Announced 10-Gbit/s NPUs
　　6.3 10-Gbit/s NPU Embedded Controllers
　　6.4 10-Gbit/s NPU Architectures
　　6.5 10-Gbit/s NPU Memory
　　6.6 10-Gbit/s NPU Interfaces
　　6.7 10-Gbit/s NPU Traffic Management

VII. PUBLIC COMPANIES
　　7.1 Agere Systems
　　7.2 AMCC
　　7.3 Broadcom
　　7.4 Freescale Semiconductor
　　7.5 Hifn
　　7.6 Intel
　　7.7 Mindspeed Technologies
　　7.8 PMC-Sierra
　　7.9 Vitesse Semiconductor

VIII. PRIVATE COMPANIES
　　8.1 Bay Microsystems
　　8.2 Cavium Networks
　　8.3 EZchip Technologies
　　8.4 Raza Microelectronics
　　8.5 Sandburst
　　8.6 Wintegra
　　8.7 Xelerated

APPENDIX
　　APPENDIX A: CONTROL-PLANE PROCESSORS
　　APPENDIX B: COMMUNICATIONS PROCESSORS
　　APPENDIX C: 2.5-GBIT/S NPUS
　　APPENDIX D: 10-GBIT/S NPUS
　　APPENDIX E: ABOUT THE AUTHOR
　　APPENDIX F: GLOSSARY
　　APPENDIX G: LEGAL DISCLAIMER

LIST OF FIGURES
　　SECTION I
　　SECTION II
　　　　Figure 2.1 Typical Network Processor Application
　　　　Figure 2.2 Network Processor Vendors
　　SECTION III
　　　　Figure 3.1 High-Performance Control-Plane Processors in Production
　　　　Figure 3.2 Latest 0.13u Control-Plane Processors
　　　　Figure 3.3 90nm Control-Plane Processors
　　　　Figure 3.4 Control-Plane Processor Estimated Performance
　　　　Figure 3.5 Typical Control-Plane Processor
　　　　Figure 3.6 Control-Plane Processor Architectures
　　　　Figure 3.7 Control-Plane Processors With Packet Interfaces
　　SECTION IV
　　　　Figure 4.1 Typical Communications Processor
　　　　Figure 4.2 Communications Processors in Production
　　　　Figure 4.3 Newly Announced Communications Processors
　　　　Figure 4.4 Communications Processor I/O
　　　　Figure 4.5 Integrated Access Device (IAD) Application
　　　　Figure 4.6 Communications Processors With Security Acceleration
　　　　Figure 4.7 Communications Processor Traffic Management
　　SECTION V
　　　　Figure 5.1 2.5-Gbit/s NPU Production Devices
　　　　Figure 5.2 Newly Announced 2.5-Gbit/s NPUs
　　　　Figure 5.3 2.5-Gbit/s NPU Embedded Controllers
　　　　Figure 5.4 A RISC-Based NPU
　　　　Figure 5.5 2.5-Gbit/s NPU Architectures
　　　　Figure 5.6 Memory Functions
　　　　Figure 5.7 2.5-Gbit/s NPU Memory and Host Interfaces
　　　　Figure 5.8 Typical 2.5-Gbit/s Line Card
　　　　Figure 5.9 2.5-Gbit/s NPU I/O
　　　　Figure 5.10 2.5-Gbit/s NPUs With Integrated Hardware Shaping
　　　　Figure 5.11 2.5-Gbit/s NPU Scheduling
　　　　Figure 5.12 2.5-Gbit/s NPU Multicast Features
　　SECTION VI
　　　　Figure 6.1 10-Gbit/s NPUs Now in Production
　　　　Figure 6.2 Newly Announced 10-Gbit/s NPUs
　　　　Figure 6.3 10-Gbit/s NPU Architectures
　　SECTION VI (CONTINUED)
　　　　Figure 6.4 A VLIW-Based NPU
　　　　Figure 6.5 10-Gbit/s NPU Memory Interfaces
　　　　Figure 6.6 10-Gbit/s NPU Interfaces
　　　　Figure 6.7 10-Gbit/s NPU Shaping
　　　　Figure 6.8 10-Gbit/s NPU Scheduling
　　SECTION VII
　　　　Figure 7.1 AMCC nP3705 Access Processor
　　　　Figure 7.2 Broadcom BCM1480 Control-Plane Processor
　　　　Figure 7.3 Freescale MPC8560 PowerQUICC III
　　　　Figure 7.4 Hifn Antero Network Processor
　　　　Figure 7.5 Intel IXP2350 Access Processor
　　　　Figure 7.6 Mindspeed M27483 Traffic Stream Processor (TSP3)
　　　　Figure 7.7 PMC-Sierra RM9000x2GL Control-Plane Processor
　　SECTION VIII
　　　　Figure 8.1 Cavium Octeon Network Services Processor
　　　　Figure 8.2 EZchip NP-2 Network Processor
　　　　Figure 8.3 Wintegra WinPath Communications Processor
　　APPENDIX A
　　　　Figure A.1 Control-Plane Processor Summary
　　　　Figure A.2 Control-Plane Processor I/O
　　APPENDIX B
　　　　Figure B.1 Communications Processor Summary
　　　　Figure B.2 Communications Processor I/O
　　　　Figure B.3 Communications Processor Features
　　APPENDIX C
　　　　Figure C.1 2.5-Gbit/s NPU Summary
　　　　Figure C.2 2.5-Gbit/s NPU Architecture
　　　　Figure C.3 2.5-Gbit/s NPU I/O
　　　　Figure C.4 2.5-Gbit/s NPU Traffic Management
　　APPENDIX D
　　　　Figure D.1 10-Gbit/s NPU Summary
　　　　Figure D.2 10-Gbit/s NPU Architecture
　　　　Figure D.3 10-Gbit/s NPU I/O
　　　　Figure D.4 10-Gbit/s NPU Traffic Management